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[/] [socgen/] [trunk/] [Makefile] - Rev 101

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101 Added new designs for minsoc release candidate
convert tool set to parse proper ip-xact

THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT		 jt_eaton 4601d 07h /socgen/trunk/Makefile
100 created workspace prroject=fpga_mrisc for single compile
general cleanup		 jt_eaton 4613d 15h /socgen/trunk/Makefile
99 moved all projects into /projects/opencores.org
added build_register
added fizzim		 jt_eaton 4656d 07h /socgen/trunk/Makefile
97 changed sim run directory to icarus
added ise directory into syn
added _tb testbench file to all sims		 jt_eaton 4692d 12h /socgen/trunk/Makefile
96 hierConnections now create ports jt_eaton 4766d 09h /socgen/trunk/Makefile
94 socgen now supports both sim and syn views
now allow each xml file to set its destination		 jt_eaton 4802d 08h /socgen/trunk/Makefile
90 now build all testbenches from ip-xact files and list as testbench in design.soc jt_eaton 4828d 08h /socgen/trunk/Makefile
83 added design.soc files
xml files now 99% 1685 complient		 jt_eaton 4925d 14h /socgen/trunk/Makefile
82 renmamed cde_synchronizers to cde_sync
added hierarchial dependency search
converted more xmp to follow ip-xact		 jt_eaton 4940d 08h /socgen/trunk/Makefile
74 split out sw Makefile into projects /bin
split out _cpu into seperate component		 jt_eaton 5008d 14h /socgen/trunk/Makefile
57 Now generate all filelists from xml files jt_eaton 5041d 10h /socgen/trunk/Makefile
56 soc_builder now builds verilog from xml files jt_eaton 5046d 18h /socgen/trunk/Makefile
54 now set up fpga targets from xml files jt_eaton 5049d 16h /socgen/trunk/Makefile
53 fixed check_fpgas jt_eaton 5052d 05h /socgen/trunk/Makefile
49 added covered code coverage
added xml descriptors
added soc_Link tool		 jt_eaton 5052d 09h /socgen/trunk/Makefile
46 removed hard coded component names from design files
define file is always defines.v
top level is always top.v		 jt_eaton 5088d 18h /socgen/trunk/Makefile
28 added T6502 processor
added vga_char_ctrl		 jt_eaton 5154d 17h /socgen/trunk/Makefile
20 added Nexys2 support
expanded docs
created tools directory		 jt_eaton 5187d 05h /socgen/trunk/Makefile
19 added serial_xmit module
updated and added docs		 jt_eaton 5194d 11h /socgen/trunk/Makefile
16 added geda scripts and symbols/sch jt_eaton 5201d 11h /socgen/trunk/Makefile

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