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[/] [socgen/] [trunk/] [Makefile] - Rev 103

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103 added user guide
resynced to local repository		 jt_eaton 4577d 07h /socgen/trunk/Makefile
102 all ip-xact files now readable by kactus2 jt_eaton 4639d 03h /socgen/trunk/Makefile
101 Added new designs for minsoc release candidate
convert tool set to parse proper ip-xact

THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT		 jt_eaton 4640d 04h /socgen/trunk/Makefile
100 created workspace prroject=fpga_mrisc for single compile
general cleanup		 jt_eaton 4652d 12h /socgen/trunk/Makefile
99 moved all projects into /projects/opencores.org
added build_register
added fizzim		 jt_eaton 4695d 05h /socgen/trunk/Makefile
97 changed sim run directory to icarus
added ise directory into syn
added _tb testbench file to all sims		 jt_eaton 4731d 10h /socgen/trunk/Makefile
96 hierConnections now create ports jt_eaton 4805d 06h /socgen/trunk/Makefile
94 socgen now supports both sim and syn views
now allow each xml file to set its destination		 jt_eaton 4841d 05h /socgen/trunk/Makefile
90 now build all testbenches from ip-xact files and list as testbench in design.soc jt_eaton 4867d 05h /socgen/trunk/Makefile
83 added design.soc files
xml files now 99% 1685 complient		 jt_eaton 4964d 12h /socgen/trunk/Makefile
82 renmamed cde_synchronizers to cde_sync
added hierarchial dependency search
converted more xmp to follow ip-xact		 jt_eaton 4979d 06h /socgen/trunk/Makefile
74 split out sw Makefile into projects /bin
split out _cpu into seperate component		 jt_eaton 5047d 11h /socgen/trunk/Makefile
57 Now generate all filelists from xml files jt_eaton 5080d 07h /socgen/trunk/Makefile
56 soc_builder now builds verilog from xml files jt_eaton 5085d 16h /socgen/trunk/Makefile
54 now set up fpga targets from xml files jt_eaton 5088d 13h /socgen/trunk/Makefile
53 fixed check_fpgas jt_eaton 5091d 02h /socgen/trunk/Makefile
49 added covered code coverage
added xml descriptors
added soc_Link tool		 jt_eaton 5091d 07h /socgen/trunk/Makefile
46 removed hard coded component names from design files
define file is always defines.v
top level is always top.v		 jt_eaton 5127d 16h /socgen/trunk/Makefile
28 added T6502 processor
added vga_char_ctrl		 jt_eaton 5193d 15h /socgen/trunk/Makefile
20 added Nexys2 support
expanded docs
created tools directory		 jt_eaton 5226d 03h /socgen/trunk/Makefile

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