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[/] [socgen/] [trunk/] [Makefile] - Rev 96

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Rev Log message Author Age Path
96 hierConnections now create ports jt_eaton 4777d 05h /socgen/trunk/Makefile
94 socgen now supports both sim and syn views
now allow each xml file to set its destination		 jt_eaton 4813d 04h /socgen/trunk/Makefile
90 now build all testbenches from ip-xact files and list as testbench in design.soc jt_eaton 4839d 04h /socgen/trunk/Makefile
83 added design.soc files
xml files now 99% 1685 complient		 jt_eaton 4936d 11h /socgen/trunk/Makefile
82 renmamed cde_synchronizers to cde_sync
added hierarchial dependency search
converted more xmp to follow ip-xact		 jt_eaton 4951d 05h /socgen/trunk/Makefile
74 split out sw Makefile into projects /bin
split out _cpu into seperate component		 jt_eaton 5019d 10h /socgen/trunk/Makefile
57 Now generate all filelists from xml files jt_eaton 5052d 06h /socgen/trunk/Makefile
56 soc_builder now builds verilog from xml files jt_eaton 5057d 15h /socgen/trunk/Makefile
54 now set up fpga targets from xml files jt_eaton 5060d 12h /socgen/trunk/Makefile
53 fixed check_fpgas jt_eaton 5063d 02h /socgen/trunk/Makefile
49 added covered code coverage
added xml descriptors
added soc_Link tool		 jt_eaton 5063d 06h /socgen/trunk/Makefile
46 removed hard coded component names from design files
define file is always defines.v
top level is always top.v		 jt_eaton 5099d 15h /socgen/trunk/Makefile
28 added T6502 processor
added vga_char_ctrl		 jt_eaton 5165d 14h /socgen/trunk/Makefile
20 added Nexys2 support
expanded docs
created tools directory		 jt_eaton 5198d 02h /socgen/trunk/Makefile
19 added serial_xmit module
updated and added docs		 jt_eaton 5205d 08h /socgen/trunk/Makefile
16 added geda scripts and symbols/sch jt_eaton 5212d 08h /socgen/trunk/Makefile
10 added impact_bat to generate svf files jt_eaton 5242d 13h /socgen/trunk/Makefile
6 added pic_micro from minirisc project with design to run code
on a digilent Basys board		 jt_eaton 5251d 09h /socgen/trunk/Makefile

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