OpenCores
URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [Projects/] [opencores.org/] [fpgas/] [ip/] [Nexys2_T6502/] [sim/] [testbenches/] [verilog/] [sram.load] - Rev 135

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
135 resynced with socgen, Release V1.0.0 changed tool lic to apache 2.0 jt_eaton 2945d 05h /socgen/trunk/Projects/opencores.org/fpgas/ip/Nexys2_T6502/sim/testbenches/verilog/sram.load
134 Resynced database
socgen now supports elaboration
Bad news is that it is now alot slower.
jt_eaton 3455d 07h /socgen/trunk/Projects/opencores.org/fpgas/ip/Nexys2_T6502/sim/testbenches/verilog/sram.load
131 Added elaboration databases and tools
Added bus map creation tools
jt_eaton 3530d 05h /socgen/trunk/Projects/opencores.org/fpgas/ip/Nexys2_T6502/sim/testbenches/verilog/sram.load

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.