URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] [sys/] [soc_link_child] - Rev 118

Rev	Log message	Author	Age	Path
118	optimized gen_verilog added padring support added configuration support added jtag sims added accellera candidate bus defs	jt_eaton	4465d 20h	/socgen/trunk/tools/sys/soc_link_child
117	added yellow pages tools	jt_eaton	4493d 15h	/socgen/trunk/tools/sys/soc_link_child
115	split or1200_cpu up into all ip-xact components removed dead files	jt_eaton	4572d 17h	/socgen/trunk/tools/sys/soc_link_child
107	added designCfg files to all modules	jt_eaton	4617d 22h	/socgen/trunk/tools/sys/soc_link_child
101	Added new designs for minsoc release candidate convert tool set to parse proper ip-xact THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT	jt_eaton	4711d 10h	/socgen/trunk/tools/sys/soc_link_child
99	moved all projects into /projects/opencores.org added build_register added fizzim	jt_eaton	4766d 10h	/socgen/trunk/tools/sys/soc_link_child
94	socgen now supports both sim and syn views now allow each xml file to set its destination	jt_eaton	4912d 11h	/socgen/trunk/tools/sys/soc_link_child