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[/] [socgen/] [trunk/] [tools/] [sys/] [workspace] - Rev 135

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Rev	Log message	Author	Age	Path
135	resynced with socgen, Release V1.0.0 changed tool lic to apache 2.0	jt_eaton	2948d 21h	/socgen/trunk/tools/sys/workspace
134	Resynced database socgen now supports elaboration Bad news is that it is now alot slower.	jt_eaton	3458d 23h	/socgen/trunk/tools/sys/workspace
133	Added Desing databases and foundation for elaborations tools	jt_eaton	3502d 00h	/socgen/trunk/tools/sys/workspace
131	Added elaboration databases and tools Added bus map creation tools	jt_eaton	3533d 21h	/socgen/trunk/tools/sys/workspace
130	Dec 2014 major release trimmed out some IP replaced perl database with Berkeley	jt_eaton	3637d 14h	/socgen/trunk/tools/sys/workspace
128	major cleanup added toolflows for sim,syn,documentation,linting and verilog added documentation tools	jt_eaton	4092d 20h	/socgen/trunk/tools/sys/workspace
127	final cleanup before DAC	jt_eaton	4207d 16h	/socgen/trunk/tools/sys/workspace
124	beta release candidate 1 changed design.xml name aligned schema with filesystem	jt_eaton	4358d 18h	/socgen/trunk/tools/sys/workspace
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4454d 14h	/socgen/trunk/tools/sys/workspace
118	optimized gen_verilog added padring support added configuration support added jtag sims added accellera candidate bus defs	jt_eaton	4489d 23h	/socgen/trunk/tools/sys/workspace
117	added yellow pages tools	jt_eaton	4517d 18h	/socgen/trunk/tools/sys/workspace
110	split out more ip-xact components added sw sources	jt_eaton	4637d 16h	/socgen/trunk/tools/sys/workspace
100	created workspace prroject=fpga_mrisc for single compile general cleanup	jt_eaton	4747d 20h	/socgen/trunk/tools/sys/workspace
99	moved all projects into /projects/opencores.org added build_register added fizzim	jt_eaton	4790d 13h	/socgen/trunk/tools/sys/workspace
97	changed sim run directory to icarus added ise directory into syn added _tb testbench file to all sims	jt_eaton	4826d 18h	/socgen/trunk/tools/sys/workspace
96	hierConnections now create ports	jt_eaton	4900d 14h	/socgen/trunk/tools/sys/workspace
95	added first cut at busdefs added clock reset enable pads and jtag_rpc	jt_eaton	4909d 12h	/socgen/trunk/tools/sys/workspace
94	socgen now supports both sim and syn views now allow each xml file to set its destination	jt_eaton	4936d 13h	/socgen/trunk/tools/sys/workspace

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