URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] [yp/] [lib.pm] - Rev 133

Rev	Log message	Author	Age	Path
133	Added Desing databases and foundation for elaborations tools	jt_eaton	3322d 01h	/socgen/trunk/tools/yp/lib.pm
131	Added elaboration databases and tools Added bus map creation tools	jt_eaton	3353d 21h	/socgen/trunk/tools/yp/lib.pm
130	Dec 2014 major release trimmed out some IP replaced perl database with Berkeley	jt_eaton	3457d 15h	/socgen/trunk/tools/yp/lib.pm
128	major cleanup added toolflows for sim,syn,documentation,linting and verilog added documentation tools	jt_eaton	3912d 21h	/socgen/trunk/tools/yp/lib.pm
127	final cleanup before DAC	jt_eaton	4027d 17h	/socgen/trunk/tools/yp/lib.pm
126	added mor1kx cleanup	jt_eaton	4080d 22h	/socgen/trunk/tools/yp/lib.pm
125	Added two new 6502 cores in www.6502.org cleaned up sogen xml files and added module name control	jt_eaton	4125d 16h	/socgen/trunk/tools/yp/lib.pm
124	beta release candidate 1 changed design.xml name aligned schema with filesystem	jt_eaton	4178d 19h	/socgen/trunk/tools/yp/lib.pm
122	Moved Nexys2 from opencores.org to digilentinc.com Moved jtag_rpc and or1k Busdefs into cde_jtag and or1200 components	jt_eaton	4201d 14h	/socgen/trunk/tools/yp/lib.pm
120	clean up componentGenerators names and directories sim + lint now synthesis TestBench	jt_eaton	4239d 20h	/socgen/trunk/tools/yp/lib.pm
118	optimized gen_verilog added padring support added configuration support added jtag sims added accellera candidate bus defs	jt_eaton	4310d 00h	/socgen/trunk/tools/yp/lib.pm
117	added yellow pages tools	jt_eaton	4337d 19h	/socgen/trunk/tools/yp/lib.pm