URL https://opencores.org/ocsvn/socgen/socgen/trunk

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[/] [socgen/] [trunk] - Rev 57

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Rev	Log message	Author	Age	Path
57	Now generate all filelists from xml files	jt_eaton	5040d 19h	/socgen/trunk
56	soc_builder now builds verilog from xml files	jt_eaton	5046d 04h	/socgen/trunk
55	removed pre-rout and gates sims	jt_eaton	5049d 00h	/socgen/trunk
54	now set up fpga targets from xml files	jt_eaton	5049d 01h	/socgen/trunk
53	fixed check_fpgas	jt_eaton	5051d 14h	/socgen/trunk
52	removed noworking sims and syn	jt_eaton	5051d 15h	/socgen/trunk
51	removed old test	jt_eaton	5051d 15h	/socgen/trunk
50	clean up from last checkin	jt_eaton	5051d 16h	/socgen/trunk
49	added covered code coverage added xml descriptors added soc_Link tool	jt_eaton	5051d 19h	/socgen/trunk
48	added support for covered code checking	jt_eaton	5074d 01h	/socgen/trunk
47	removed old variant	jt_eaton	5088d 04h	/socgen/trunk
46	removed hard coded component names from design files define file is always defines.v top level is always top.v	jt_eaton	5088d 04h	/socgen/trunk
45	added 6502 sims/software and synth	jt_eaton	5095d 00h	/socgen/trunk
44	added new parts and sw for 6502	jt_eaton	5095d 03h	/socgen/trunk
43	complete rework of states and sequencer added interrupts moved prog space and vectors to F space	jt_eaton	5105d 01h	/socgen/trunk
42	removed old versions that used prog as C space	jt_eaton	5105d 01h	/socgen/trunk
41	added kim-1 design and program now support Nexys2 sdram	jt_eaton	5123d 02h	/socgen/trunk
40	removed test for deleted block	jt_eaton	5123d 02h	/socgen/trunk
39	added io_probe to sims added boot rom into 6502 added T6502_control	jt_eaton	5131d 14h	/socgen/trunk
38	fsm level removed	jt_eaton	5131d 15h	/socgen/trunk

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[/] [socgen/] [trunk] - Rev 57

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