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[/] [socgen/] [trunk] - Rev 59

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Rev Log message Author Age Path
59 added filelist.core to syn dirs to customize core jt_eaton 5069d 20h /socgen/trunk
58 removed old Makefiles jt_eaton 5070d 11h /socgen/trunk
57 Now generate all filelists from xml files jt_eaton 5070d 11h /socgen/trunk
56 soc_builder now builds verilog from xml files jt_eaton 5075d 20h /socgen/trunk
55 removed pre-rout and gates sims jt_eaton 5078d 16h /socgen/trunk
54 now set up fpga targets from xml files jt_eaton 5078d 17h /socgen/trunk
53 fixed check_fpgas jt_eaton 5081d 06h /socgen/trunk
52 removed noworking sims and syn jt_eaton 5081d 07h /socgen/trunk
51 removed old test jt_eaton 5081d 07h /socgen/trunk
50 clean up from last checkin jt_eaton 5081d 08h /socgen/trunk
49 added covered code coverage
added xml descriptors
added soc_Link tool		 jt_eaton 5081d 11h /socgen/trunk
48 added support for covered code checking jt_eaton 5103d 17h /socgen/trunk
47 removed old variant jt_eaton 5117d 20h /socgen/trunk
46 removed hard coded component names from design files
define file is always defines.v
top level is always top.v		 jt_eaton 5117d 20h /socgen/trunk
45 added 6502 sims/software and synth jt_eaton 5124d 16h /socgen/trunk
44 added new parts and sw for 6502 jt_eaton 5124d 19h /socgen/trunk
43 complete rework of states and sequencer
added interrupts
moved prog space and vectors to F space		 jt_eaton 5134d 17h /socgen/trunk
42 removed old versions that used prog as C space jt_eaton 5134d 17h /socgen/trunk
41 added kim-1 design and program
now support Nexys2 sdram		 jt_eaton 5152d 18h /socgen/trunk
40 removed test for deleted block jt_eaton 5152d 18h /socgen/trunk

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