URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk] - Rev 65

Rev	Log message	Author	Age	Path
65	added params.sim to sims updated install's	jt_eaton	5031d 16h	/socgen/trunk
64	added support for Fedora 13	jt_eaton	5035d 15h	/socgen/trunk
63	added install config for Ubuntu 10.10	jt_eaton	5035d 21h	/socgen/trunk
62	fixed parameters from `defines	jt_eaton	5039d 13h	/socgen/trunk
61	now generate dut files for coverage removed use of lndir	jt_eaton	5039d 15h	/socgen/trunk
60	moved alu_logic into seperate component	jt_eaton	5040d 02h	/socgen/trunk
59	added filelist.core to syn dirs to customize core	jt_eaton	5040d 02h	/socgen/trunk
58	removed old Makefiles	jt_eaton	5040d 17h	/socgen/trunk
57	Now generate all filelists from xml files	jt_eaton	5040d 18h	/socgen/trunk
56	soc_builder now builds verilog from xml files	jt_eaton	5046d 02h	/socgen/trunk
55	removed pre-rout and gates sims	jt_eaton	5048d 23h	/socgen/trunk
54	now set up fpga targets from xml files	jt_eaton	5049d 00h	/socgen/trunk
53	fixed check_fpgas	jt_eaton	5051d 13h	/socgen/trunk
52	removed noworking sims and syn	jt_eaton	5051d 14h	/socgen/trunk
51	removed old test	jt_eaton	5051d 14h	/socgen/trunk
50	clean up from last checkin	jt_eaton	5051d 14h	/socgen/trunk
49	added covered code coverage added xml descriptors added soc_Link tool	jt_eaton	5051d 17h	/socgen/trunk
48	added support for covered code checking	jt_eaton	5073d 23h	/socgen/trunk
47	removed old variant	jt_eaton	5088d 02h	/socgen/trunk
46	removed hard coded component names from design files define file is always defines.v top level is always top.v	jt_eaton	5088d 02h	/socgen/trunk