URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk] - Rev 69

Rev	Log message	Author	Age	Path
69	added work dir	jt_eaton	5052d 07h	/socgen/trunk
68	moved to seperate components	jt_eaton	5055d 07h	/socgen/trunk
67	updated installs	jt_eaton	5055d 07h	/socgen/trunk
66	converted sims to use parameters added msp and 6502 software installs	jt_eaton	5056d 06h	/socgen/trunk
65	added params.sim to sims updated install's	jt_eaton	5061d 07h	/socgen/trunk
64	added support for Fedora 13	jt_eaton	5065d 06h	/socgen/trunk
63	added install config for Ubuntu 10.10	jt_eaton	5065d 12h	/socgen/trunk
62	fixed parameters from `defines	jt_eaton	5069d 04h	/socgen/trunk
61	now generate dut files for coverage removed use of lndir	jt_eaton	5069d 06h	/socgen/trunk
60	moved alu_logic into seperate component	jt_eaton	5069d 17h	/socgen/trunk
59	added filelist.core to syn dirs to customize core	jt_eaton	5069d 17h	/socgen/trunk
58	removed old Makefiles	jt_eaton	5070d 08h	/socgen/trunk
57	Now generate all filelists from xml files	jt_eaton	5070d 09h	/socgen/trunk
56	soc_builder now builds verilog from xml files	jt_eaton	5075d 17h	/socgen/trunk
55	removed pre-rout and gates sims	jt_eaton	5078d 14h	/socgen/trunk
54	now set up fpga targets from xml files	jt_eaton	5078d 15h	/socgen/trunk
53	fixed check_fpgas	jt_eaton	5081d 04h	/socgen/trunk
52	removed noworking sims and syn	jt_eaton	5081d 05h	/socgen/trunk
51	removed old test	jt_eaton	5081d 05h	/socgen/trunk
50	clean up from last checkin	jt_eaton	5081d 05h	/socgen/trunk