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[/] [socgen] - Rev 135

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135 resynced with socgen, Release V1.0.0 changed tool lic to apache 2.0 jt_eaton 2808d 06h /socgen
134 Resynced database
socgen now supports elaboration
Bad news is that it is now alot slower.		 jt_eaton 3318d 08h /socgen
133 Added Desing databases and foundation for elaborations tools jt_eaton 3361d 09h /socgen
132 fixed permissions on tools/bin jt_eaton 3393d 05h /socgen
131 Added elaboration databases and tools
Added bus map creation tools		 jt_eaton 3393d 06h /socgen
130 Dec 2014 major release
trimmed out some IP
replaced perl database with Berkeley		 jt_eaton 3496d 23h /socgen
129 removed unneeded 6502 files jt_eaton 3952d 05h /socgen
128 major cleanup
added toolflows for sim,syn,documentation,linting and verilog
added documentation tools		 jt_eaton 3952d 05h /socgen
127 final cleanup before DAC jt_eaton 4067d 01h /socgen
126 added mor1kx
cleanup		 jt_eaton 4120d 06h /socgen
125 Added two new 6502 cores in www.6502.org

cleaned up sogen xml files and added module name control		 jt_eaton 4165d 00h /socgen
124 beta release candidate 1
changed design.xml name
aligned schema with filesystem		 jt_eaton 4218d 03h /socgen
123 added support for ubuntu 12.10 jt_eaton 4232d 19h /socgen
122 Moved Nexys2 from opencores.org to digilentinc.com
Moved jtag_rpc and or1k Busdefs into cde_jtag and or1200 components		 jt_eaton 4240d 22h /socgen
121 cleaned up sims, added autogenerated test bench files
removed mrisc and experimental or1k code		 jt_eaton 4261d 04h /socgen
120 clean up componentGenerators names and directories
sim + lint now synthesis TestBench		 jt_eaton 4279d 04h /socgen
119 moved copyright files into /verilog
changed cde copyright to apache from gplv3
split out tools into separate subdirectories
changed design.xml files to socgen: namespace		 jt_eaton 4313d 23h /socgen
118 optimized gen_verilog
added padring support
added configuration support
added jtag sims
added accellera candidate bus defs		 jt_eaton 4349d 08h /socgen
117 added yellow pages tools jt_eaton 4377d 03h /socgen
116 added build_header
now use build_register for all spr components
resynced or1200 code back to use orbuild toolchain		 jt_eaton 4412d 00h /socgen

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