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[/] [socgen] - Rev 119

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Rev Log message Author Age Path
119 moved copyright files into /verilog
changed cde copyright to apache from gplv3
split out tools into separate subdirectories
changed design.xml files to socgen: namespace		 jt_eaton 4408d 22h /socgen
118 optimized gen_verilog
added padring support
added configuration support
added jtag sims
added accellera candidate bus defs		 jt_eaton 4444d 07h /socgen
117 added yellow pages tools jt_eaton 4472d 02h /socgen
116 added build_header
now use build_register for all spr components
resynced or1200 code back to use orbuild toolchain		 jt_eaton 4506d 23h /socgen
115 split or1200_cpu up into all ip-xact components
removed dead files		 jt_eaton 4551d 04h /socgen
114 moved or1200 connectivity out of verilog and into ip-xact
added or1200_boot block
removed force of 00 on lowest iwb_addr bits		 jt_eaton 4563d 04h /socgen
113 started refactoring or1200 jt_eaton 4568d 20h /socgen
112 added more test sims
removed unneeded files		 jt_eaton 4578d 09h /socgen
111 split or1200 out into seperate test suite jt_eaton 4580d 03h /socgen
110 split out more ip-xact components
added sw sources		 jt_eaton 4592d 01h /socgen
109 removed unused file jt_eaton 4595d 00h /socgen
108 removed unneeded files jt_eaton 4596d 07h /socgen
107 added designCfg files to all modules jt_eaton 4596d 09h /socgen
106 checked in orp_soc project step 2 jt_eaton 4602d 02h /socgen
105 moved or1200_monitor from testbench to dut jt_eaton 4604d 23h /socgen
104 fixed search in preprocessor script
added initial orp_soc project		 jt_eaton 4606d 23h /socgen
103 added user guide
resynced to local repository		 jt_eaton 4627d 00h /socgen
102 all ip-xact files now readable by kactus2 jt_eaton 4688d 19h /socgen
101 Added new designs for minsoc release candidate
convert tool set to parse proper ip-xact

THIS WILL BREAK ALL THE OLD DESIGNS UNTIL I FIX THEIR IP_XACT		 jt_eaton 4689d 21h /socgen
100 created workspace prroject=fpga_mrisc for single compile
general cleanup		 jt_eaton 4702d 05h /socgen

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