URL https://opencores.org/ocsvn/spi/spi/trunk

Subversion Repositories spi

[/] [spi/] [tags/] [rel_5/] [rtl/] [verilog/] [spi_defines.v] - Rev 27

Rev	Log message	Author	Age	Path
27	New directory structure.	root	5630d 02h	/spi/tags/rel_5/rtl/verilog/spi_defines.v
18	This commit was manufactured by cvs2svn to create tag 'rel_5'.		7705d 21h	/spi/tags/rel_5/rtl/verilog/spi_defines.v
17	Define mess fixed.	simons	7705d 21h	/spi/tags/rel_5/rtl/verilog/spi_defines.v
15	Defines set in order.	simons	7706d 01h	/spi/tags/rel_5/rtl/verilog/spi_defines.v
13	8-bit WB access enabled.	simons	7706d 18h	/spi/tags/rel_5/rtl/verilog/spi_defines.v
9	Support for 128 bits character length added. Zero value divider bug fixed.	simons	7785d 18h	/spi/tags/rel_5/rtl/verilog/spi_defines.v
8	Automatic slave select signal generation added.	simons	7805d 19h	/spi/tags/rel_5/rtl/verilog/spi_defines.v
7	Support for 64 bit caharacter len added.	simons	7894d 08h	/spi/tags/rel_5/rtl/verilog/spi_defines.v
2	Initial import	simons	8092d 20h	/spi/tags/rel_5/rtl/verilog/spi_defines.v