URL https://opencores.org/ocsvn/spi/spi/trunk

Subversion Repositories spi

[/] [spi/] [trunk/] [rtl/] [verilog/] [spi_defines.v] - Rev 27

Rev	Log message	Author	Age	Path
27	New directory structure.	root	5622d 08h	/spi/trunk/rtl/verilog/spi_defines.v
25	CTRL register bit fields changed, VATS testing support added.	simons	7443d 00h	/spi/trunk/rtl/verilog/spi_defines.v
17	Define mess fixed.	simons	7698d 03h	/spi/trunk/rtl/verilog/spi_defines.v
15	Defines set in order.	simons	7698d 07h	/spi/trunk/rtl/verilog/spi_defines.v
13	8-bit WB access enabled.	simons	7699d 00h	/spi/trunk/rtl/verilog/spi_defines.v
9	Support for 128 bits character length added. Zero value divider bug fixed.	simons	7778d 01h	/spi/trunk/rtl/verilog/spi_defines.v
8	Automatic slave select signal generation added.	simons	7798d 02h	/spi/trunk/rtl/verilog/spi_defines.v
7	Support for 64 bit caharacter len added.	simons	7886d 14h	/spi/trunk/rtl/verilog/spi_defines.v
2	Initial import	simons	8085d 02h	/spi/trunk/rtl/verilog/spi_defines.v