URL https://opencores.org/ocsvn/srdydrdy_lib/srdydrdy_lib/trunk

Subversion Repositories srdydrdy_lib

[/] [srdydrdy_lib/] [trunk/] [rtl/] [verilog/] [forks] - Rev 30

Rev	Log message	Author	Age	Path
30	Added llmanager component	ghutchis	4542d 18h	/srdydrdy_lib/trunk/rtl/verilog/forks
29	Updated arbitration	ghutchis	4857d 17h	/srdydrdy_lib/trunk/rtl/verilog/forks
24	Added CRC32 checker to environment & RTL	ghutchis	5186d 09h	/srdydrdy_lib/trunk/rtl/verilog/forks
21	Changed rrslow to rrmux, updated descriptions, changed bridge mux to fast arb	ghutchis	5383d 14h	/srdydrdy_lib/trunk/rtl/verilog/forks
20	Added fast arb mode	ghutchis	5383d 16h	/srdydrdy_lib/trunk/rtl/verilog/forks
18	Added scoreboard and scoreboard testbench	ghutchis	5384d 08h	/srdydrdy_lib/trunk/rtl/verilog/forks
14	- Modified large FIFO to remove "full" signal and store only N-1 words - changed small FIFO to use memory instance instead of registers - changed sequence generator to enable more complex tests - changed sd_mirror to use combinatorial assign output	ghutchis	5387d 03h	/srdydrdy_lib/trunk/rtl/verilog/forks
10	Fixed "locked" variable in rrslow	ghutchis	5392d 16h	/srdydrdy_lib/trunk/rtl/verilog/forks
7	Added rrslow	ghutchis	5396d 08h	/srdydrdy_lib/trunk/rtl/verilog/forks
2	Initial commit of directory structure and basic components	ghutchis	5405d 12h	/srdydrdy_lib/trunk/rtl/verilog/forks