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[/] [sxp/] [trunk] - Rev 59

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Rev Log message Author Age Path
59 New directory structure. root 5567d 19h /sxp/trunk
58 removed safe_switch from module (not needed) samg 8210d 12h /trunk
57 removed saf_switch from int_cont module samg 8210d 12h /trunk
56 rewrite with one less interface signal and simplification of verilog code samg 8210d 12h /trunk
55 simplified regf_status interface samg 8210d 12h /trunk
54 fixed case statement, sensitivity list samg 8213d 03h /trunk
53 comment spelling fix samg 8213d 03h /trunk
52 minor expression rewrite in 4th stage samg 8218d 13h /trunk
51 Rewrote verilog for write enable signals for different destinations in the last stage.
The code is much easier to read and more liner to follow.		 samg 8219d 11h /trunk
50 fixed sensitivity list error in last pipeline stage samg 8219d 23h /trunk
49 changed run script name and added instructions samg 8219d 23h /trunk
48 fixed neg edge event trigger samg 8219d 23h /trunk
47 changed prefix from ~| to ! (same thing) samg 8219d 23h /trunk
46 vcd dumpvar captures all levels samg 8222d 10h /trunk
45 Fixed bug in 16 bit data swap instruction.
The instructions were making the regf status module look at reg 0
even though reg 0 didn't have anything to do with the purpose of
the instruction. Made reg b addr field mirror reg a field.
This error caused unecessary stalls.
Performance increase caused by calling instruction correctly and
not causing stalls from mal-formed instructions.		 samg 8222d 10h /trunk
44 - Removed #1 delay (was originally put in for debug)
- Stall signal forced low during pipeline flush.
(No effect on functionality but it is easier to look at
the waveforms during debug)		 samg 8222d 10h /trunk
43 integrated common rams into processor samg 8246d 04h /trunk
42 minor header correction samg 8246d 04h /trunk
41 common rams samg 8246d 04h /trunk
40 added header and parameter restructure samg 8246d 05h /trunk

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