URL https://opencores.org/ocsvn/t400/t400/trunk

Subversion Repositories t400

[/] [t400/] [trunk/] [bench/] [vhdl] - Rev 144

Rev	Log message	Author	Age	Path
144	initial check-in	arniml	6695d 21h	/t400/trunk/bench/vhdl
139	initial check-in	arniml	6696d 05h	/t400/trunk/bench/vhdl
125	initial check-in	arniml	6697d 00h	/t400/trunk/bench/vhdl
117	initial check-in	arniml	6701d 22h	/t400/trunk/bench/vhdl
105	remove obsolete en_clk_s	arniml	6702d 00h	/t400/trunk/bench/vhdl
104	fix typo	arniml	6702d 04h	/t400/trunk/bench/vhdl
97	lower nibble is OD to prevent contention with testbench	arniml	6709d 20h	/t400/trunk/bench/vhdl
91	don't generate interrupt when in interrupt routine around 0x100	arniml	6710d 03h	/t400/trunk/bench/vhdl
78	provide SA at L port	arniml	6710d 16h	/t400/trunk/bench/vhdl
73	use 'after' instead of wait for signal delay should resolve problems with delta cycle arrival times	arniml	6710d 20h	/t400/trunk/bench/vhdl
67	explicitly select clock divider 4	arniml	6711d 00h	/t400/trunk/bench/vhdl
66	explicitly select clock divider 8	arniml	6711d 00h	/t400/trunk/bench/vhdl
65	add global signals for testbench instrumentation	arniml	6711d 00h	/t400/trunk/bench/vhdl
64	add fail reporting for port d	arniml	6711d 00h	/t400/trunk/bench/vhdl
63	initial check-in	arniml	6711d 00h	/t400/trunk/bench/vhdl
60	connect cko_i to bit 2 of IN bus	arniml	6714d 18h	/t400/trunk/bench/vhdl
58	consider IN port	arniml	6715d 18h	/t400/trunk/bench/vhdl
57	consider CKO and IN port	arniml	6715d 18h	/t400/trunk/bench/vhdl
56	drive IN port	arniml	6715d 18h	/t400/trunk/bench/vhdl
31	extend D-port checks	arniml	6720d 19h	/t400/trunk/bench/vhdl