URL https://opencores.org/ocsvn/t400/t400/trunk

Subversion Repositories t400

[/] [t400/] [trunk/] [rtl] - Rev 52

Rev	Log message	Author	Age	Path
52	+ reset neg_edge flip-flops to '1' -> after por, a 1-to-0 edge is required to trigger the latches initially + use to_X01	arniml	6754d 15h	/t400/trunk/rtl
49	io_in added	arniml	6755d 16h	/t400/trunk/rtl
48	instructions ININ and INIL implemented	arniml	6755d 16h	/t400/trunk/rtl
47	simplify ININ/INIL instruction support	arniml	6755d 16h	/t400/trunk/rtl
46	operations for IN port added	arniml	6755d 16h	/t400/trunk/rtl
45	initial check-in	arniml	6755d 16h	/t400/trunk/rtl
43	route cko to ALU for INIL instruction	arniml	6755d 19h	/t400/trunk/rtl
39	select CK divide by 8	arniml	6757d 14h	/t400/trunk/rtl
37	timer module included	arniml	6757d 14h	/t400/trunk/rtl
36	skip-on-timer implemented	arniml	6757d 14h	/t400/trunk/rtl
35	initial check-in	arniml	6757d 14h	/t400/trunk/rtl
27	connect missing input direction for IO G	arniml	6760d 16h	/t400/trunk/rtl
15	initial check-in	arniml	6762d 18h	/t400/trunk/rtl
14	t420 hierarchies added	arniml	6762d 18h	/t400/trunk/rtl
13	hand-down clock divider option	arniml	6769d 14h	/t400/trunk/rtl
12	fix sensitivity list	arniml	6770d 14h	/t400/trunk/rtl
11	renamed to rtl	arniml	6770d 15h	/t400/trunk/rtl
10	renamed t400_por configuration to rtl	arniml	6770d 15h	/t400/trunk/rtl
9	initial check-in	arniml	6770d 15h	/t400/trunk/rtl
8	phi1_en_q is dedicated enable for PHI1 clock to suppress glitches on sk_o	arniml	6771d 03h	/t400/trunk/rtl