OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_1_beta/] [KNOWN_BUGS] - Rev 117

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
117 add bug
Program Memory bank can be switched during interrupt		 arniml 7301d 11h /t48/tags/rel_0_1_beta/KNOWN_BUGS
109 add new bug for release 0.1 BETA arniml 7341d 10h /t48/tags/rel_0_1_beta/KNOWN_BUGS
105 initial check-in
describe bugs of release 0.1 BETA		 arniml 7343d 20h /t48/tags/rel_0_1_beta/KNOWN_BUGS

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.