URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_1_beta/] [KNOWN_BUGS] - Rev 212

Rev	Log message	Author	Age	Path
212	add bug reports "Problem when INT and JMP" "P2 Port value restored after expander access"	arniml	6811d 17h	/t48/tags/rel_0_1_beta/KNOWN_BUGS
189	add bug report "Target address of JMP and CALL to Program Memory Bank 1 corrupted by interrupt"	arniml	6861d 17h	/t48/tags/rel_0_1_beta/KNOWN_BUGS
175	add bug report "MSB of Program Counter changed upon PC increment"	arniml	6958d 19h	/t48/tags/rel_0_1_beta/KNOWN_BUGS
163	add bug Wrong clock applied to T0	arniml	6993d 18h	/t48/tags/rel_0_1_beta/KNOWN_BUGS
146	add bug RD' and WR' not asserted for INS A, BUS and OUTL BUS, A	arniml	7184d 17h	/t48/tags/rel_0_1_beta/KNOWN_BUGS
139	add bug P1 constantly in push-pull mode in t8048	arniml	7186d 05h	/t48/tags/rel_0_1_beta/KNOWN_BUGS
135	add bug PSENn Timing	arniml	7228d 04h	/t48/tags/rel_0_1_beta/KNOWN_BUGS
121	update bug description for Program Memory bank can be switched during interrupt	arniml	7301d 17h	/t48/tags/rel_0_1_beta/KNOWN_BUGS
117	add bug Program Memory bank can be switched during interrupt	arniml	7302d 18h	/t48/tags/rel_0_1_beta/KNOWN_BUGS
109	add new bug for release 0.1 BETA	arniml	7342d 16h	/t48/tags/rel_0_1_beta/KNOWN_BUGS
105	initial check-in describe bugs of release 0.1 BETA	arniml	7345d 02h	/t48/tags/rel_0_1_beta/KNOWN_BUGS