URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_3_beta/] [bench/] [vhdl/] [tb_t8048.vhd] - Rev 329

Rev	Log message	Author	Age	Path
292	New directory structure.	root	5599d 09h	/t48/tags/rel_0_3_beta/bench/vhdl/tb_t8048.vhd
253	This commit was manufactured by cvs2svn to create tag 'rel_0_3_beta'.		6569d 18h	/t48/tags/rel_0_3_beta/bench/vhdl/tb_t8048.vhd
68	connect T0 and T1 to P1	arniml	7386d 00h	/t48/tags/rel_0_3_beta/bench/vhdl/tb_t8048.vhd
56	wait for instruction strobe after final end-of-simulation detection this ensures that the last mov instruction is part of the dump and enables 100% matching with i8039 simulator	arniml	7389d 22h	/t48/tags/rel_0_3_beta/bench/vhdl/tb_t8048.vhd
19	enhance simulation result string	arniml	7408d 20h	/t48/tags/rel_0_3_beta/bench/vhdl/tb_t8048.vhd
8	initial check-in	arniml	7410d 21h	/t48/tags/rel_0_3_beta/bench/vhdl/tb_t8048.vhd