URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_3_beta/] [rtl/] [vhdl/] [timer.vhd] - Rev 292

Rev	Log message	Author	Age	Path
292	New directory structure.	root	5607d 13h	/t48/tags/rel_0_3_beta/rtl/vhdl/timer.vhd
253	This commit was manufactured by cvs2svn to create tag 'rel_0_3_beta'.		6577d 21h	/t48/tags/rel_0_3_beta/rtl/vhdl/timer.vhd
129	cleanup copyright notice	arniml	7310d 06h	/t48/tags/rel_0_3_beta/rtl/vhdl/timer.vhd
128	counter_q is not cleared during reset this would match all different descriptions of the Counter as a) if the software assumes that the Counter is modified during reset, it will initialize the Counter anyhow b) the special case 'Counter not modified during reset' is covered	arniml	7317d 09h	/t48/tags/rel_0_3_beta/rtl/vhdl/timer.vhd
91	fix edge detector bug for counter	arniml	7366d 07h	/t48/tags/rel_0_3_beta/rtl/vhdl/timer.vhd
59	increment prescaler with MSTATE4	arniml	7397d 00h	/t48/tags/rel_0_3_beta/rtl/vhdl/timer.vhd
4	initial check-in	arniml	7420d 01h	/t48/tags/rel_0_3_beta/rtl/vhdl/timer.vhd