OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_3_beta/] [sw/] - Rev 292

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
292 New directory structure. root 5623d 02h /t48/tags/rel_0_3_beta/sw
253 This commit was manufactured by cvs2svn to create tag 'rel_0_3_beta'. 6593d 11h /t48/tags/rel_0_3_beta/sw
127 + log status of A11 properly during interrupt routines
+ trigger counter on negative edge of T1 instead of positive edge		 arniml 7333d 00h /t48/tags/rel_0_3_beta/sw
126 + specify hex file for external ROM on i8039 command line
+ support for no_dump_compare file in test cell		 arniml 7333d 00h /t48/tags/rel_0_3_beta/sw
125 exclude from dump compare arniml 7333d 00h /t48/tags/rel_0_3_beta/sw
124 fix wrong handling of MB after return from interrupt arniml 7333d 21h /t48/tags/rel_0_3_beta/sw
123 support hex file for external ROM arniml 7333d 21h /t48/tags/rel_0_3_beta/sw
122 test MB after return from interrupt arniml 7333d 21h /t48/tags/rel_0_3_beta/sw
118 test MB/interrupt behaviour according to bug report
"Program Memory bank can be switched during interrupt"		 arniml 7336d 15h /t48/tags/rel_0_3_beta/sw
113 generate two ROM files based on address:
+ 0 - 2047 : 2k internal ROM
+ 2048 - 4095 : 2k external ROM		 arniml 7377d 00h /t48/tags/rel_0_3_beta/sw
104 add white_box directory to test suite arniml 7380d 21h /t48/tags/rel_0_3_beta/sw
102 update for changes in address space of external memory arniml 7380d 21h /t48/tags/rel_0_3_beta/sw
99 initial check-in arniml 7380d 21h /t48/tags/rel_0_3_beta/sw
97 initial check-in arniml 7380d 22h /t48/tags/rel_0_3_beta/sw
96 select dedicated directorie(s) for regression arniml 7381d 19h /t48/tags/rel_0_3_beta/sw
95 check counter inactivity arniml 7381d 19h /t48/tags/rel_0_3_beta/sw
94 initial check-in arniml 7381d 19h /t48/tags/rel_0_3_beta/sw
90 intial check-in arniml 7381d 20h /t48/tags/rel_0_3_beta/sw
89 initial check-in arniml 7395d 17h /t48/tags/rel_0_3_beta/sw
88 allow memory bank switching during interrupts arniml 7396d 19h /t48/tags/rel_0_3_beta/sw

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.