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[/] [t48/] [tags/] [rel_0_6_beta/] [bench] - Rev 183

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Rev Log message Author Age Path
183 fix missing assignment to outclock arniml 6887d 01h /t48/tags/rel_0_6_beta/bench
160 add others to case statement arniml 7164d 22h /t48/tags/rel_0_6_beta/bench
140 remove tAW sanity check
conflicts with OUTL A, BUS		 arniml 7203d 23h /t48/tags/rel_0_6_beta/bench
133 add checks for PSEN arniml 7247d 18h /t48/tags/rel_0_6_beta/bench
111 split 4k internal ROM into
+ 2k internal ROM
+ 2k external ROM
EA of t48_core is driven by MSB of internal ROM address
if upper 2k block is selected, the system switches to EA mode on the fly		 arniml 7361d 07h /t48/tags/rel_0_6_beta/bench
110 exchange syn_rom for lpm_rom arniml 7361d 07h /t48/tags/rel_0_6_beta/bench
103 add testbench peripherals for P1 and P2
this became necessary to observe a difference between externally applied
port data and internally applied port data		 arniml 7365d 04h /t48/tags/rel_0_6_beta/bench
83 connect if_timing to P2 output of T48 arniml 7386d 22h /t48/tags/rel_0_6_beta/bench
82 check expander timings arniml 7386d 22h /t48/tags/rel_0_6_beta/bench
81 initial check-in arniml 7387d 02h /t48/tags/rel_0_6_beta/bench
80 added if_timing arniml 7387d 02h /t48/tags/rel_0_6_beta/bench
68 connect T0 and T1 to P1 arniml 7393d 23h /t48/tags/rel_0_6_beta/bench
67 initial check-in arniml 7393d 23h /t48/tags/rel_0_6_beta/bench
56 wait for instruction strobe after final end-of-simulation detection
this ensures that the last mov instruction is part of the dump and
enables 100% matching with i8039 simulator		 arniml 7397d 21h /t48/tags/rel_0_6_beta/bench
33 rename pX_limp to pX_low_imp arniml 7413d 23h /t48/tags/rel_0_6_beta/bench
30 connect prog_n_o arniml 7414d 21h /t48/tags/rel_0_6_beta/bench
19 enhance simulation result string arniml 7416d 20h /t48/tags/rel_0_6_beta/bench
10 put ext_ram on falling clock edge to sample the write enable proberly arniml 7418d 19h /t48/tags/rel_0_6_beta/bench
8 initial check-in arniml 7418d 21h /t48/tags/rel_0_6_beta/bench

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