OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_6_beta/] [rtl/] - Rev 292

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
292 New directory structure. root 5639d 14h /t48/tags/rel_0_6_beta/rtl
258 This commit was manufactured by cvs2svn to create tag 'rel_0_6_beta'. 6609d 22h /t48/tags/rel_0_6_beta/rtl
188 move check for int_pending_s into ea_i_='0' branch
this fixes a glitch on PCH when an interrutp occurs
during external program memory fetch		 arniml 6913d 02h /t48/tags/rel_0_6_beta/rtl
187 Fix bug reports:
"Target address of JMP to Program Memory Bank 1 corrupted by interrupt"
"Return address of CALL to Program Memory Bank 1 corrupted by interrupt"
int_in_progress_o was active one cycle before int_pending_o is
asserted. this confused the mb multiplexer which determines the state of
the memory bank selection flag		 arniml 6913d 03h /t48/tags/rel_0_6_beta/rtl
183 fix missing assignment to outclock arniml 6919d 06h /t48/tags/rel_0_6_beta/rtl
180 introduce prefix 't48_' for wb_master entity and configuration arniml 7007d 13h /t48/tags/rel_0_6_beta/rtl
179 introduce prefix 't48_' for all packages, entities and configurations arniml 7007d 13h /t48/tags/rel_0_6_beta/rtl
178 Move latching of BUS to MSTATE2
-> sample BUS at the end of RD'		 arniml 7009d 01h /t48/tags/rel_0_6_beta/rtl
177 Implement db_dir_o glitch-safe arniml 7009d 01h /t48/tags/rel_0_6_beta/rtl
176 Use en_clk_i instead of xtal3_s for generation of external signals.
This is required when the core runs with full xtal clock instead
of xtal/3 (xtal_div_3_g = 0).		 arniml 7009d 01h /t48/tags/rel_0_6_beta/rtl
174 fix bug report
"MSB of Program Counter changed upon PC increment"		 arniml 7010d 04h /t48/tags/rel_0_6_beta/rtl
172 save data from wishbone bus in register bank with wb_ack
necessary to hold data from peripheral/memory until it is read by T48		 arniml 7039d 01h /t48/tags/rel_0_6_beta/rtl
171 remove obsolete output stack_high_o arniml 7040d 01h /t48/tags/rel_0_6_beta/rtl
169 initial check-in arniml 7041d 13h /t48/tags/rel_0_6_beta/rtl
168 change address range of wb_master arniml 7041d 13h /t48/tags/rel_0_6_beta/rtl
167 simplify address range:
- configuration range
- Wishbone range		 arniml 7041d 13h /t48/tags/rel_0_6_beta/rtl
166 assign default for state_s arniml 7043d 05h /t48/tags/rel_0_6_beta/rtl
165 add component wb_master.vhd arniml 7044d 04h /t48/tags/rel_0_6_beta/rtl
164 initial check-in arniml 7044d 04h /t48/tags/rel_0_6_beta/rtl
162 Fix bug report:
"Wrong clock applied to T0"
t0_o is generated inside clock_ctrl with a separate flip-flop running
with xtal_i		 arniml 7045d 03h /t48/tags/rel_0_6_beta/rtl

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.