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[/] [t48/] [tags/] [rel_0_6_beta] - Rev 167

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Rev Log message Author Age Path
167 simplify address range:
- configuration range
- Wishbone range		 arniml 7003d 05h /t48/tags/rel_0_6_beta
166 assign default for state_s arniml 7004d 21h /t48/tags/rel_0_6_beta
165 add component wb_master.vhd arniml 7005d 20h /t48/tags/rel_0_6_beta
164 initial check-in arniml 7005d 20h /t48/tags/rel_0_6_beta
163 add bug
Wrong clock applied to T0		 arniml 7006d 20h /t48/tags/rel_0_6_beta
162 Fix bug report:
"Wrong clock applied to T0"
t0_o is generated inside clock_ctrl with a separate flip-flop running
with xtal_i		 arniml 7006d 20h /t48/tags/rel_0_6_beta
161 fix syntax problem that triggers an error with GHDL 0.18 arniml 7038d 00h /t48/tags/rel_0_6_beta
160 add others to case statement arniml 7158d 20h /t48/tags/rel_0_6_beta
159 fix dependencies for tb_t8048_behav_c0 and tb_t8039_behav_c0 arniml 7158d 20h /t48/tags/rel_0_6_beta
158 added hierarchies t8039_notri and t8048_notri arniml 7158d 20h /t48/tags/rel_0_6_beta
157 removed obsolete constant arniml 7158d 20h /t48/tags/rel_0_6_beta
156 added hierarchy t8039_notri arniml 7158d 20h /t48/tags/rel_0_6_beta
155 initial check-in arniml 7158d 20h /t48/tags/rel_0_6_beta
154 added t8039_notri hierarchy arniml 7158d 20h /t48/tags/rel_0_6_beta
153 introduced generic gate_port_input_g
forces masking of P1 and P2 input bus		 arniml 7159d 18h /t48/tags/rel_0_6_beta
152 added hierarchy t8048_notri and system components package arniml 7160d 09h /t48/tags/rel_0_6_beta
151 added hierarchy t8048_notri and components package for t48 systems arniml 7160d 09h /t48/tags/rel_0_6_beta
150 intruduced hierarchy t8048_notri where all system functionality
except bidirectional ports is handled		 arniml 7160d 17h /t48/tags/rel_0_6_beta
149 update arniml 7160d 17h /t48/tags/rel_0_6_beta
148 initial check-in arniml 7160d 17h /t48/tags/rel_0_6_beta

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