URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_0/] [rtl/] [vhdl/] [system/] [wb_master.vhd] - Rev 172

Rev	Log message	Author	Age	Path
172	save data from wishbone bus in register bank with wb_ack necessary to hold data from peripheral/memory until it is read by T48	arniml	7000d 19h	/t48/tags/rel_1_0/rtl/vhdl/system/wb_master.vhd
167	simplify address range: - configuration range - Wishbone range	arniml	7003d 07h	/t48/tags/rel_1_0/rtl/vhdl/system/wb_master.vhd
166	assign default for state_s	arniml	7004d 23h	/t48/tags/rel_1_0/rtl/vhdl/system/wb_master.vhd
164	initial check-in	arniml	7005d 22h	/t48/tags/rel_1_0/rtl/vhdl/system/wb_master.vhd