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[/] [t48/] [tags/] [rel_1_0/] [rtl/] [vhdl] - Rev 171

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Rev Log message Author Age Path
171 remove obsolete output stack_high_o arniml 7028d 11h /t48/tags/rel_1_0/rtl/vhdl
169 initial check-in arniml 7029d 22h /t48/tags/rel_1_0/rtl/vhdl
168 change address range of wb_master arniml 7029d 22h /t48/tags/rel_1_0/rtl/vhdl
167 simplify address range:
- configuration range
- Wishbone range		 arniml 7029d 22h /t48/tags/rel_1_0/rtl/vhdl
166 assign default for state_s arniml 7031d 14h /t48/tags/rel_1_0/rtl/vhdl
165 add component wb_master.vhd arniml 7032d 13h /t48/tags/rel_1_0/rtl/vhdl
164 initial check-in arniml 7032d 13h /t48/tags/rel_1_0/rtl/vhdl
162 Fix bug report:
"Wrong clock applied to T0"
t0_o is generated inside clock_ctrl with a separate flip-flop running
with xtal_i		 arniml 7033d 13h /t48/tags/rel_1_0/rtl/vhdl
161 fix syntax problem that triggers an error with GHDL 0.18 arniml 7064d 17h /t48/tags/rel_1_0/rtl/vhdl
157 removed obsolete constant arniml 7185d 13h /t48/tags/rel_1_0/rtl/vhdl
156 added hierarchy t8039_notri arniml 7185d 13h /t48/tags/rel_1_0/rtl/vhdl
155 initial check-in arniml 7185d 13h /t48/tags/rel_1_0/rtl/vhdl
153 introduced generic gate_port_input_g
forces masking of P1 and P2 input bus		 arniml 7186d 11h /t48/tags/rel_1_0/rtl/vhdl
150 intruduced hierarchy t8048_notri where all system functionality
except bidirectional ports is handled		 arniml 7187d 10h /t48/tags/rel_1_0/rtl/vhdl
149 update arniml 7187d 10h /t48/tags/rel_1_0/rtl/vhdl
148 initial check-in arniml 7187d 10h /t48/tags/rel_1_0/rtl/vhdl
145 remove PROG and end of XTAL2, see comment for details arniml 7224d 13h /t48/tags/rel_1_0/rtl/vhdl
144 delay db_dir_o by one machine cycle
this fixes the timing relation between BUS data and WR'		 arniml 7224d 13h /t48/tags/rel_1_0/rtl/vhdl
143 Fix bug report:
"RD' and WR' not asserted for INS A, BUS and OUTL BUS, A"
rd is asserted for INS A, BUS
wr is asserted for OUTL BUS, A
P1, P2 and BUS are written in first instruction cycle		 arniml 7224d 13h /t48/tags/rel_1_0/rtl/vhdl
142 deassert rd_q, wr_q and prog_q at end of XTAL3 arniml 7224d 13h /t48/tags/rel_1_0/rtl/vhdl

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