URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_0/] [sim/] [rtl_sim/] [Makefile.hier] - Rev 232

Rev	Log message	Author	Age	Path
232	update to new memory concept	arniml	6597d 11h	/t48/tags/rel_1_0/sim/rtl_sim/Makefile.hier
218	simplifications	arniml	6684d 18h	/t48/tags/rel_1_0/sim/rtl_sim/Makefile.hier
198	fix package dependencies	arniml	6828d 19h	/t48/tags/rel_1_0/sim/rtl_sim/Makefile.hier
159	fix dependencies for tb_t8048_behav_c0 and tb_t8039_behav_c0	arniml	7161d 16h	/t48/tags/rel_1_0/sim/rtl_sim/Makefile.hier
154	added t8039_notri hierarchy	arniml	7161d 16h	/t48/tags/rel_1_0/sim/rtl_sim/Makefile.hier
151	added hierarchy t8048_notri and components package for t48 systems	arniml	7163d 05h	/t48/tags/rel_1_0/sim/rtl_sim/Makefile.hier
112	update tb_behav_c0 for new ROM layout	arniml	7358d 00h	/t48/tags/rel_1_0/sim/rtl_sim/Makefile.hier
79	add if_timing module	arniml	7383d 19h	/t48/tags/rel_1_0/sim/rtl_sim/Makefile.hier
71	add T8039 and its testbench	arniml	7390d 17h	/t48/tags/rel_1_0/sim/rtl_sim/Makefile.hier
55	add dependency to tb_behav_pack for decoder	arniml	7394d 15h	/t48/tags/rel_1_0/sim/rtl_sim/Makefile.hier
31	refer PROJECT_DIR variable	arniml	7410d 16h	/t48/tags/rel_1_0/sim/rtl_sim/Makefile.hier
11	add description	arniml	7414d 14h	/t48/tags/rel_1_0/sim/rtl_sim/Makefile.hier
9	initial check-in	arniml	7415d 12h	/t48/tags/rel_1_0/sim/rtl_sim/Makefile.hier