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[/] [t48/] [tags/] [rel_1_0] - Rev 180

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Rev Log message Author Age Path
180 introduce prefix 't48_' for wb_master entity and configuration arniml 7004d 17h /t48/tags/rel_1_0
179 introduce prefix 't48_' for all packages, entities and configurations arniml 7004d 17h /t48/tags/rel_1_0
178 Move latching of BUS to MSTATE2
-> sample BUS at the end of RD'		 arniml 7006d 05h /t48/tags/rel_1_0
177 Implement db_dir_o glitch-safe arniml 7006d 05h /t48/tags/rel_1_0
176 Use en_clk_i instead of xtal3_s for generation of external signals.
This is required when the core runs with full xtal clock instead
of xtal/3 (xtal_div_3_g = 0).		 arniml 7006d 05h /t48/tags/rel_1_0
175 add bug report
"MSB of Program Counter changed upon PC increment"		 arniml 7007d 08h /t48/tags/rel_1_0
174 fix bug report
"MSB of Program Counter changed upon PC increment"		 arniml 7007d 08h /t48/tags/rel_1_0
173 testcase for bug report
"MSB of Program Counter changed upon PC increment"		 arniml 7007d 09h /t48/tags/rel_1_0
172 save data from wishbone bus in register bank with wb_ack
necessary to hold data from peripheral/memory until it is read by T48		 arniml 7036d 05h /t48/tags/rel_1_0
171 remove obsolete output stack_high_o arniml 7037d 05h /t48/tags/rel_1_0
170 intermediate update arniml 7038d 12h /t48/tags/rel_1_0
169 initial check-in arniml 7038d 17h /t48/tags/rel_1_0
168 change address range of wb_master arniml 7038d 17h /t48/tags/rel_1_0
167 simplify address range:
- configuration range
- Wishbone range		 arniml 7038d 17h /t48/tags/rel_1_0
166 assign default for state_s arniml 7040d 09h /t48/tags/rel_1_0
165 add component wb_master.vhd arniml 7041d 08h /t48/tags/rel_1_0
164 initial check-in arniml 7041d 08h /t48/tags/rel_1_0
163 add bug
Wrong clock applied to T0		 arniml 7042d 07h /t48/tags/rel_1_0
162 Fix bug report:
"Wrong clock applied to T0"
t0_o is generated inside clock_ctrl with a separate flip-flop running
with xtal_i		 arniml 7042d 07h /t48/tags/rel_1_0
161 fix syntax problem that triggers an error with GHDL 0.18 arniml 7073d 12h /t48/tags/rel_1_0

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