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[/] [t48/] [tags/] [rel_1_0] - Rev 29

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Rev Log message Author Age Path
29 take auxiliary carry from direct ALU connection arniml 7443d 16h /t48/tags/rel_1_0
28 update wiring for DA support arniml 7443d 17h /t48/tags/rel_1_0
27 implemented mnemonic DA arniml 7443d 17h /t48/tags/rel_1_0
26 support for DA instruction arniml 7443d 17h /t48/tags/rel_1_0
25 initial check-in arniml 7443d 17h /t48/tags/rel_1_0
24 connect control signal for Port 2 expander arniml 7444d 01h /t48/tags/rel_1_0
23 rework Port 2 expander handling arniml 7444d 01h /t48/tags/rel_1_0
22 merge MN_ANLD, MN_MOVD_PP_A and MN_ORLD_PP_A to OUTLD_PP_A arniml 7444d 01h /t48/tags/rel_1_0
21 implement mnemonics:
+ MOVD_A_PP
+ OUTD_PP_A -> ANLD PP, A; MOVD PP, A; ORLD PP, A		 arniml 7444d 01h /t48/tags/rel_1_0
20 move code for PROG out of if-branch for xtal3_s arniml 7444d 01h /t48/tags/rel_1_0
19 enhance simulation result string arniml 7445d 15h /t48/tags/rel_1_0
18 fix constant format arniml 7445d 15h /t48/tags/rel_1_0
17 fix test arniml 7445d 15h /t48/tags/rel_1_0
16 fix header arniml 7445d 15h /t48/tags/rel_1_0
15 initial check-in arniml 7446d 14h /t48/tags/rel_1_0
14 initial check-in arniml 7446d 15h /t48/tags/rel_1_0
12 Imported sources arniml 7446d 15h /t48/tags/rel_1_0
11 add description arniml 7446d 16h /t48/tags/rel_1_0
10 put ext_ram on falling clock edge to sample the write enable proberly arniml 7447d 15h /t48/tags/rel_1_0
9 initial check-in arniml 7447d 15h /t48/tags/rel_1_0

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