URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_0] - Rev 59

Rev	Log message	Author	Age	Path
59	increment prescaler with MSTATE4	arniml	7396d 01h	/t48/tags/rel_1_0
58	add periodic interrupt	arniml	7396d 01h	/t48/tags/rel_1_0
57	abort if no interrupt occurs	arniml	7396d 01h	/t48/tags/rel_1_0
56	wait for instruction strobe after final end-of-simulation detection this ensures that the last mov instruction is part of the dump and enables 100% matching with i8039 simulator	arniml	7397d 02h	/t48/tags/rel_1_0
55	add dependency to tb_behav_pack for decoder	arniml	7397d 02h	/t48/tags/rel_1_0
54	- add tb_istrobe_s	arniml	7397d 02h	/t48/tags/rel_1_0
53	make istrobe visible through testbench package	arniml	7397d 02h	/t48/tags/rel_1_0
52	+ fix bug in PSW[3] + read SP properly for dump	arniml	7397d 02h	/t48/tags/rel_1_0
51	+ implement Port1 and Port2 + connect T0 and T1 + return proper program memory contents	arniml	7397d 02h	/t48/tags/rel_1_0
49	Imported sources	arniml	7402d 03h	/t48/tags/rel_1_0
48	update copyright notice	arniml	7402d 03h	/t48/tags/rel_1_0
47	initial check-in	arniml	7402d 03h	/t48/tags/rel_1_0
46	fix test	arniml	7404d 01h	/t48/tags/rel_1_0
45	remove unused signals	arniml	7404d 01h	/t48/tags/rel_1_0
44	default assignment for aux_carry_o	arniml	7404d 02h	/t48/tags/rel_1_0
43	fix sensitivity list	arniml	7405d 02h	/t48/tags/rel_1_0
42	change test values that match better to the test case	arniml	7405d 04h	/t48/tags/rel_1_0
41	expand PATH	arniml	7405d 05h	/t48/tags/rel_1_0
40	rework adder and force resource sharing between ADD, INC and DEC	arniml	7405d 05h	/t48/tags/rel_1_0
39	initial check-in	arniml	7407d 08h	/t48/tags/rel_1_0