URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_0] - Rev 85

Rev	Log message	Author	Age	Path
85	initial check-in	arniml	7408d 21h	/t48/tags/rel_1_0
84	add if_timing module	arniml	7414d 12h	/t48/tags/rel_1_0
83	connect if_timing to P2 output of T48	arniml	7414d 12h	/t48/tags/rel_1_0
82	check expander timings	arniml	7414d 12h	/t48/tags/rel_1_0
81	initial check-in	arniml	7414d 17h	/t48/tags/rel_1_0
80	added if_timing	arniml	7414d 17h	/t48/tags/rel_1_0
79	add if_timing module	arniml	7414d 17h	/t48/tags/rel_1_0
78	adjust external timing of BUS	arniml	7414d 17h	/t48/tags/rel_1_0
77	move from std_logic_arith to numeric_std	arniml	7415d 09h	/t48/tags/rel_1_0
76	initial check-in	arniml	7415d 13h	/t48/tags/rel_1_0
75	remove obsolete design unit	arniml	7415d 13h	/t48/tags/rel_1_0
74	enhance pass/fail detection	arniml	7415d 22h	/t48/tags/rel_1_0
73	removed dummy_s - workaround not longer needed for GHDL 0.11.1	arniml	7415d 22h	/t48/tags/rel_1_0
72	removed superfluous signal from sensitivity list	arniml	7415d 22h	/t48/tags/rel_1_0
71	add T8039 and its testbench	arniml	7421d 14h	/t48/tags/rel_1_0
70	clean test cell before make	arniml	7421d 14h	/t48/tags/rel_1_0
69	fix name of istrobe	arniml	7421d 14h	/t48/tags/rel_1_0
68	connect T0 and T1 to P1	arniml	7421d 14h	/t48/tags/rel_1_0
67	initial check-in	arniml	7421d 14h	/t48/tags/rel_1_0
66	add temporary workaround for GHDL 0.11	arniml	7421d 14h	/t48/tags/rel_1_0