URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_1/] [sw/] [verif] - Rev 265

Rev	Log message	Author	Age	Path
265	tagging changed for io expander simulation	arniml	6601d 02h	/t48/tags/rel_1_1/sw/verif
264	initial check-in	arniml	6601d 02h	/t48/tags/rel_1_1/sw/verif
246	initial check-in	arniml	6606d 01h	/t48/tags/rel_1_1/sw/verif
245	initial check-in	arniml	6606d 02h	/t48/tags/rel_1_1/sw/verif
239	adapt t48 external ROM offset	arniml	6624d 00h	/t48/tags/rel_1_1/sw/verif
238	initial check-in	arniml	6624d 00h	/t48/tags/rel_1_1/sw/verif
237	initial check-in	arniml	6624d 00h	/t48/tags/rel_1_1/sw/verif
236	initial check-in	arniml	6624d 01h	/t48/tags/rel_1_1/sw/verif
229	rework hex/simulation targets	arniml	6627d 00h	/t48/tags/rel_1_1/sw/verif
199	initial check-in	arniml	6858d 04h	/t48/tags/rel_1_1/sw/verif
194	initial check-in	arniml	6859d 15h	/t48/tags/rel_1_1/sw/verif
185	initial check-in	arniml	6913d 03h	/t48/tags/rel_1_1/sw/verif
184	initial check-in	arniml	6913d 05h	/t48/tags/rel_1_1/sw/verif
173	testcase for bug report "MSB of Program Counter changed upon PC increment"	arniml	7004d 06h	/t48/tags/rel_1_1/sw/verif
141	disable external memory to avoid conflicts with outl a, bus	arniml	7230d 06h	/t48/tags/rel_1_1/sw/verif
131	update	arniml	7274d 01h	/t48/tags/rel_1_1/sw/verif
130	initial check-in	arniml	7274d 01h	/t48/tags/rel_1_1/sw/verif
125	exclude from dump compare	arniml	7343d 13h	/t48/tags/rel_1_1/sw/verif
122	test MB after return from interrupt	arniml	7344d 10h	/t48/tags/rel_1_1/sw/verif
118	test MB/interrupt behaviour according to bug report "Program Memory bank can be switched during interrupt"	arniml	7347d 04h	/t48/tags/rel_1_1/sw/verif