URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_1] - Rev 79

Rev	Log message	Author	Age	Path
79	add if_timing module	arniml	7386d 00h	/t48/tags/rel_1_1
78	adjust external timing of BUS	arniml	7386d 00h	/t48/tags/rel_1_1
77	move from std_logic_arith to numeric_std	arniml	7386d 17h	/t48/tags/rel_1_1
76	initial check-in	arniml	7386d 21h	/t48/tags/rel_1_1
75	remove obsolete design unit	arniml	7386d 21h	/t48/tags/rel_1_1
74	enhance pass/fail detection	arniml	7387d 05h	/t48/tags/rel_1_1
73	removed dummy_s - workaround not longer needed for GHDL 0.11.1	arniml	7387d 05h	/t48/tags/rel_1_1
72	removed superfluous signal from sensitivity list	arniml	7387d 05h	/t48/tags/rel_1_1
71	add T8039 and its testbench	arniml	7392d 22h	/t48/tags/rel_1_1
70	clean test cell before make	arniml	7392d 22h	/t48/tags/rel_1_1
69	fix name of istrobe	arniml	7392d 22h	/t48/tags/rel_1_1
68	connect T0 and T1 to P1	arniml	7392d 22h	/t48/tags/rel_1_1
67	initial check-in	arniml	7392d 22h	/t48/tags/rel_1_1
66	add temporary workaround for GHDL 0.11	arniml	7392d 22h	/t48/tags/rel_1_1
65	clean up sensitivity list	arniml	7392d 22h	/t48/tags/rel_1_1
64	+ enhance instruction strobe generation + rework address output under EA=1 conditions	arniml	7392d 22h	/t48/tags/rel_1_1
63	reset machine state to MSTATE3 to allow proper instruction fetch after reset	arniml	7392d 22h	/t48/tags/rel_1_1
62	initial check-in	arniml	7392d 22h	/t48/tags/rel_1_1
61	expand script for dump compare	arniml	7394d 18h	/t48/tags/rel_1_1
60	+ add marker for injected calls + suppress intstruction strobes for injected calls	arniml	7395d 19h	/t48/tags/rel_1_1