URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_1] - Rev 85

Rev	Log message	Author	Age	Path
85	initial check-in	arniml	7380d 05h	/t48/tags/rel_1_1
84	add if_timing module	arniml	7385d 20h	/t48/tags/rel_1_1
83	connect if_timing to P2 output of T48	arniml	7385d 21h	/t48/tags/rel_1_1
82	check expander timings	arniml	7385d 21h	/t48/tags/rel_1_1
81	initial check-in	arniml	7386d 01h	/t48/tags/rel_1_1
80	added if_timing	arniml	7386d 01h	/t48/tags/rel_1_1
79	add if_timing module	arniml	7386d 01h	/t48/tags/rel_1_1
78	adjust external timing of BUS	arniml	7386d 01h	/t48/tags/rel_1_1
77	move from std_logic_arith to numeric_std	arniml	7386d 17h	/t48/tags/rel_1_1
76	initial check-in	arniml	7386d 21h	/t48/tags/rel_1_1
75	remove obsolete design unit	arniml	7386d 21h	/t48/tags/rel_1_1
74	enhance pass/fail detection	arniml	7387d 06h	/t48/tags/rel_1_1
73	removed dummy_s - workaround not longer needed for GHDL 0.11.1	arniml	7387d 06h	/t48/tags/rel_1_1
72	removed superfluous signal from sensitivity list	arniml	7387d 06h	/t48/tags/rel_1_1
71	add T8039 and its testbench	arniml	7392d 22h	/t48/tags/rel_1_1
70	clean test cell before make	arniml	7392d 22h	/t48/tags/rel_1_1
69	fix name of istrobe	arniml	7392d 22h	/t48/tags/rel_1_1
68	connect T0 and T1 to P1	arniml	7392d 22h	/t48/tags/rel_1_1
67	initial check-in	arniml	7392d 22h	/t48/tags/rel_1_1
66	add temporary workaround for GHDL 0.11	arniml	7392d 22h	/t48/tags/rel_1_1