OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_4] - Rev 130

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
130 initial check-in arniml 7275d 05h /t48/tags/rel_1_4
129 cleanup copyright notice arniml 7337d 13h /t48/tags/rel_1_4
128 counter_q is not cleared during reset
this would match all different descriptions of the Counter as
a) if the software assumes that the Counter is modified during reset, it
will initialize the Counter anyhow
b) the special case 'Counter not modified during reset' is covered		 arniml 7344d 16h /t48/tags/rel_1_4
127 + log status of A11 properly during interrupt routines
+ trigger counter on negative edge of T1 instead of positive edge		 arniml 7344d 17h /t48/tags/rel_1_4
126 + specify hex file for external ROM on i8039 command line
+ support for no_dump_compare file in test cell		 arniml 7344d 17h /t48/tags/rel_1_4
125 exclude from dump compare arniml 7344d 17h /t48/tags/rel_1_4
124 fix wrong handling of MB after return from interrupt arniml 7345d 15h /t48/tags/rel_1_4
123 support hex file for external ROM arniml 7345d 15h /t48/tags/rel_1_4
122 test MB after return from interrupt arniml 7345d 15h /t48/tags/rel_1_4
121 update bug description for
Program Memory bank can be switched during interrupt		 arniml 7348d 08h /t48/tags/rel_1_4
120 Fix bug report:
"Program Memory bank can be switched during interrupt"
int module emits int_in_progress signal that is used inside the decoder
to hold mb low for JMP and CALL during interrupts		 arniml 7348d 08h /t48/tags/rel_1_4
119 add int_in_progress_o to entity of int module arniml 7348d 08h /t48/tags/rel_1_4
118 test MB/interrupt behaviour according to bug report
"Program Memory bank can be switched during interrupt"		 arniml 7348d 08h /t48/tags/rel_1_4
117 add bug
Program Memory bank can be switched during interrupt		 arniml 7349d 09h /t48/tags/rel_1_4
116 adapt to GHDL 0.12 / gcc 3.4.0 arniml 7377d 09h /t48/tags/rel_1_4
115 extend description arniml 7378d 13h /t48/tags/rel_1_4
114 initial check-in arniml 7382d 09h /t48/tags/rel_1_4
113 generate two ROM files based on address:
+ 0 - 2047 : 2k internal ROM
+ 2048 - 4095 : 2k external ROM		 arniml 7388d 18h /t48/tags/rel_1_4
112 update tb_behav_c0 for new ROM layout arniml 7388d 18h /t48/tags/rel_1_4
111 split 4k internal ROM into
+ 2k internal ROM
+ 2k external ROM
EA of t48_core is driven by MSB of internal ROM address
if upper 2k block is selected, the system switches to EA mode on the fly		 arniml 7388d 18h /t48/tags/rel_1_4

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.