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[/] [t48/] [tags/] [rel_1_4] - Rev 148

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Rev Log message Author Age Path
148 initial check-in arniml 7193d 18h /t48/tags/rel_1_4
147 initial check-in for release 0.5 BETA arniml 7229d 19h /t48/tags/rel_1_4
146 add bug
RD' and WR' not asserted for INS A, BUS and OUTL BUS, A		 arniml 7230d 19h /t48/tags/rel_1_4
145 remove PROG and end of XTAL2, see comment for details arniml 7230d 20h /t48/tags/rel_1_4
144 delay db_dir_o by one machine cycle
this fixes the timing relation between BUS data and WR'		 arniml 7230d 20h /t48/tags/rel_1_4
143 Fix bug report:
"RD' and WR' not asserted for INS A, BUS and OUTL BUS, A"
rd is asserted for INS A, BUS
wr is asserted for OUTL BUS, A
P1, P2 and BUS are written in first instruction cycle		 arniml 7230d 21h /t48/tags/rel_1_4
142 deassert rd_q, wr_q and prog_q at end of XTAL3 arniml 7230d 21h /t48/tags/rel_1_4
141 disable external memory to avoid conflicts with outl a, bus arniml 7230d 21h /t48/tags/rel_1_4
140 remove tAW sanity check
conflicts with OUTL A, BUS		 arniml 7230d 21h /t48/tags/rel_1_4
139 add bug
P1 constantly in push-pull mode in t8048		 arniml 7232d 07h /t48/tags/rel_1_4
138 Fix for:
P1 constantly in push-pull mode in t8048		 arniml 7232d 07h /t48/tags/rel_1_4
137 add link to COMPILE_LIST arniml 7269d 20h /t48/tags/rel_1_4
136 initial check-in arniml 7269d 20h /t48/tags/rel_1_4
135 add bug
PSENn Timing		 arniml 7274d 06h /t48/tags/rel_1_4
134 Fix bug report:
"PSENn Timing"
PSEN is now only asserted for the second cycle if explicitely
requested by assert_psen_s.
The previous implementation asserted PSEN together with RD or WR.		 arniml 7274d 16h /t48/tags/rel_1_4
133 add checks for PSEN arniml 7274d 16h /t48/tags/rel_1_4
132 stop simulation upon assertion error arniml 7274d 16h /t48/tags/rel_1_4
131 update arniml 7274d 16h /t48/tags/rel_1_4
130 initial check-in arniml 7274d 16h /t48/tags/rel_1_4
129 cleanup copyright notice arniml 7337d 00h /t48/tags/rel_1_4

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