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[/] [t48/] [tags/] [rel_1_4] - Rev 184

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Rev Log message Author Age Path
184 initial check-in arniml 6884d 10h /t48/tags/rel_1_4
183 fix missing assignment to outclock arniml 6884d 13h /t48/tags/rel_1_4
182 intermediate version arniml 6964d 11h /t48/tags/rel_1_4
181 fix typo arniml 6964d 14h /t48/tags/rel_1_4
180 introduce prefix 't48_' for wb_master entity and configuration arniml 6972d 20h /t48/tags/rel_1_4
179 introduce prefix 't48_' for all packages, entities and configurations arniml 6972d 20h /t48/tags/rel_1_4
178 Move latching of BUS to MSTATE2
-> sample BUS at the end of RD'		 arniml 6974d 08h /t48/tags/rel_1_4
177 Implement db_dir_o glitch-safe arniml 6974d 08h /t48/tags/rel_1_4
176 Use en_clk_i instead of xtal3_s for generation of external signals.
This is required when the core runs with full xtal clock instead
of xtal/3 (xtal_div_3_g = 0).		 arniml 6974d 08h /t48/tags/rel_1_4
175 add bug report
"MSB of Program Counter changed upon PC increment"		 arniml 6975d 11h /t48/tags/rel_1_4
174 fix bug report
"MSB of Program Counter changed upon PC increment"		 arniml 6975d 11h /t48/tags/rel_1_4
173 testcase for bug report
"MSB of Program Counter changed upon PC increment"		 arniml 6975d 11h /t48/tags/rel_1_4
172 save data from wishbone bus in register bank with wb_ack
necessary to hold data from peripheral/memory until it is read by T48		 arniml 7004d 08h /t48/tags/rel_1_4
171 remove obsolete output stack_high_o arniml 7005d 08h /t48/tags/rel_1_4
170 intermediate update arniml 7006d 14h /t48/tags/rel_1_4
169 initial check-in arniml 7006d 20h /t48/tags/rel_1_4
168 change address range of wb_master arniml 7006d 20h /t48/tags/rel_1_4
167 simplify address range:
- configuration range
- Wishbone range		 arniml 7006d 20h /t48/tags/rel_1_4
166 assign default for state_s arniml 7008d 11h /t48/tags/rel_1_4
165 add component wb_master.vhd arniml 7009d 10h /t48/tags/rel_1_4

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