URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_4] - Rev 25

Rev	Log message	Author	Age	Path
25	initial check-in	arniml	7413d 03h	/t48/tags/rel_1_4
24	connect control signal for Port 2 expander	arniml	7413d 11h	/t48/tags/rel_1_4
23	rework Port 2 expander handling	arniml	7413d 11h	/t48/tags/rel_1_4
22	merge MN_ANLD, MN_MOVD_PP_A and MN_ORLD_PP_A to OUTLD_PP_A	arniml	7413d 11h	/t48/tags/rel_1_4
21	implement mnemonics: + MOVD_A_PP + OUTD_PP_A -> ANLD PP, A; MOVD PP, A; ORLD PP, A	arniml	7413d 11h	/t48/tags/rel_1_4
20	move code for PROG out of if-branch for xtal3_s	arniml	7413d 12h	/t48/tags/rel_1_4
19	enhance simulation result string	arniml	7415d 02h	/t48/tags/rel_1_4
18	fix constant format	arniml	7415d 02h	/t48/tags/rel_1_4
17	fix test	arniml	7415d 02h	/t48/tags/rel_1_4
16	fix header	arniml	7415d 02h	/t48/tags/rel_1_4
15	initial check-in	arniml	7416d 01h	/t48/tags/rel_1_4
14	initial check-in	arniml	7416d 02h	/t48/tags/rel_1_4
12	Imported sources	arniml	7416d 02h	/t48/tags/rel_1_4
11	add description	arniml	7416d 03h	/t48/tags/rel_1_4
10	put ext_ram on falling clock edge to sample the write enable proberly	arniml	7417d 01h	/t48/tags/rel_1_4
9	initial check-in	arniml	7417d 01h	/t48/tags/rel_1_4
8	initial check-in	arniml	7417d 03h	/t48/tags/rel_1_4
7	initial check-in	arniml	7417d 03h	/t48/tags/rel_1_4
6	moved to system directory	arniml	7417d 03h	/t48/tags/rel_1_4
5	initial check-in	arniml	7418d 03h	/t48/tags/rel_1_4