URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_4] - Rev 30

Rev	Log message	Author	Age	Path
30	connect prog_n_o	arniml	7442d 00h	/t48/tags/rel_1_4
29	take auxiliary carry from direct ALU connection	arniml	7442d 00h	/t48/tags/rel_1_4
28	update wiring for DA support	arniml	7442d 00h	/t48/tags/rel_1_4
27	implemented mnemonic DA	arniml	7442d 01h	/t48/tags/rel_1_4
26	support for DA instruction	arniml	7442d 01h	/t48/tags/rel_1_4
25	initial check-in	arniml	7442d 01h	/t48/tags/rel_1_4
24	connect control signal for Port 2 expander	arniml	7442d 09h	/t48/tags/rel_1_4
23	rework Port 2 expander handling	arniml	7442d 09h	/t48/tags/rel_1_4
22	merge MN_ANLD, MN_MOVD_PP_A and MN_ORLD_PP_A to OUTLD_PP_A	arniml	7442d 09h	/t48/tags/rel_1_4
21	implement mnemonics: + MOVD_A_PP + OUTD_PP_A -> ANLD PP, A; MOVD PP, A; ORLD PP, A	arniml	7442d 09h	/t48/tags/rel_1_4
20	move code for PROG out of if-branch for xtal3_s	arniml	7442d 09h	/t48/tags/rel_1_4
19	enhance simulation result string	arniml	7443d 23h	/t48/tags/rel_1_4
18	fix constant format	arniml	7443d 23h	/t48/tags/rel_1_4
17	fix test	arniml	7443d 23h	/t48/tags/rel_1_4
16	fix header	arniml	7443d 23h	/t48/tags/rel_1_4
15	initial check-in	arniml	7444d 22h	/t48/tags/rel_1_4
14	initial check-in	arniml	7444d 23h	/t48/tags/rel_1_4
12	Imported sources	arniml	7444d 23h	/t48/tags/rel_1_4
11	add description	arniml	7445d 00h	/t48/tags/rel_1_4
10	put ext_ram on falling clock edge to sample the write enable proberly	arniml	7445d 23h	/t48/tags/rel_1_4