URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_4] - Rev 57

Rev	Log message	Author	Age	Path
57	abort if no interrupt occurs	arniml	7394d 14h	/t48/tags/rel_1_4
56	wait for instruction strobe after final end-of-simulation detection this ensures that the last mov instruction is part of the dump and enables 100% matching with i8039 simulator	arniml	7395d 15h	/t48/tags/rel_1_4
55	add dependency to tb_behav_pack for decoder	arniml	7395d 15h	/t48/tags/rel_1_4
54	- add tb_istrobe_s	arniml	7395d 15h	/t48/tags/rel_1_4
53	make istrobe visible through testbench package	arniml	7395d 15h	/t48/tags/rel_1_4
52	+ fix bug in PSW[3] + read SP properly for dump	arniml	7395d 15h	/t48/tags/rel_1_4
51	+ implement Port1 and Port2 + connect T0 and T1 + return proper program memory contents	arniml	7395d 15h	/t48/tags/rel_1_4
49	Imported sources	arniml	7400d 16h	/t48/tags/rel_1_4
48	update copyright notice	arniml	7400d 16h	/t48/tags/rel_1_4
47	initial check-in	arniml	7400d 16h	/t48/tags/rel_1_4
46	fix test	arniml	7402d 13h	/t48/tags/rel_1_4
45	remove unused signals	arniml	7402d 13h	/t48/tags/rel_1_4
44	default assignment for aux_carry_o	arniml	7402d 15h	/t48/tags/rel_1_4
43	fix sensitivity list	arniml	7403d 15h	/t48/tags/rel_1_4
42	change test values that match better to the test case	arniml	7403d 17h	/t48/tags/rel_1_4
41	expand PATH	arniml	7403d 17h	/t48/tags/rel_1_4
40	rework adder and force resource sharing between ADD, INC and DEC	arniml	7403d 17h	/t48/tags/rel_1_4
39	initial check-in	arniml	7405d 21h	/t48/tags/rel_1_4
38	add measures to implement XCHD	arniml	7405d 21h	/t48/tags/rel_1_4
37	add dump_compare support	arniml	7405d 21h	/t48/tags/rel_1_4