URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 258

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Rev	Log message	Author	Age	Path
258	Fixed the input parametric testing logic, removed a pad.	creep	5546d 19h	/t6507lp/trunk/rtl/verilog
255	Changed the PADS verilog description to minimize violations	creep	5568d 22h	/t6507lp/trunk/rtl/verilog
254	Fixed a latch in the design	creep	5568d 22h	/t6507lp/trunk/rtl/verilog
253	Changed the rw_mem signal name in the hierarchy	creep	5591d 22h	/t6507lp/trunk/rtl/verilog
252	Added a stubs file for the pads.	creep	5591d 22h	/t6507lp/trunk/rtl/verilog
251	Added the io wrapper	creep	5592d 01h	/t6507lp/trunk/rtl/verilog
246	Added some older files plus the first syn script	creep	5599d 01h	/t6507lp/trunk/rtl/verilog
243	Fixing STA_IDY bug	creep	5640d 18h	/t6507lp/trunk/rtl/verilog
242	Bug regardind the STA_IDY opcode	creep	5640d 22h	/t6507lp/trunk/rtl/verilog
239	Zero flag fixed for SBC while in Decimal Mode. Bug #34.	gabrieloshiro	5641d 23h	/t6507lp/trunk/rtl/verilog
238	ALU file is linted.	creep	5644d 21h	/t6507lp/trunk/rtl/verilog
237	Added a preliminary collision detection logic.	creep	5645d 22h	/t6507lp/trunk/rtl/verilog
236	Added the video converter testbench to the repository.	creep	5646d 01h	/t6507lp/trunk/rtl/verilog
235	Bug #60: added a brief simulation to the video_converter module.	creep	5646d 19h	/t6507lp/trunk/rtl/verilog
234	SBC Decimal mode 100% verified.	creep	5651d 20h	/t6507lp/trunk/rtl/verilog
233	ADC and SBC are 100% verified in regular mode. Decimal mode still missing.	creep	5652d 00h	/t6507lp/trunk/rtl/verilog
232	New video test.	creep	5653d 18h	/t6507lp/trunk/rtl/verilog
231	Minor bugs fixed.	gabrieloshiro	5653d 20h	/t6507lp/trunk/rtl/verilog
230	Changed TIA behavior. It is now pixel-based.	creep	5653d 20h	/t6507lp/trunk/rtl/verilog
229	Created a one-line pattern.	creep	5654d 01h	/t6507lp/trunk/rtl/verilog

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Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] - Rev 258

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