URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu.v] - Rev 152

Rev	Log message	Author	Age	Path
152	Bug #24 from trac was fixed.	gabrieloshiro	5585d 22h	/t6507lp/trunk/rtl/verilog/t6507lp_alu.v
151	tah comitado!	gabrieloshiro	5585d 23h	/t6507lp/trunk/rtl/verilog/t6507lp_alu.v
150	Bug #24 from trac might be fixed. Processor register is working properly.	gabrieloshiro	5585d 23h	/t6507lp/trunk/rtl/verilog/t6507lp_alu.v
149	Bug #24 from trac might be fixed. Processor register is working properly.	gabrieloshiro	5586d 00h	/t6507lp/trunk/rtl/verilog/t6507lp_alu.v
148	Reset assertion was commented. It was not working properly.	gabrieloshiro	5586d 00h	/t6507lp/trunk/rtl/verilog/t6507lp_alu.v
145	ASL instruction fixed. For some reason the operator "<<" is not working properly.	gabrieloshiro	5586d 23h	/t6507lp/trunk/rtl/verilog/t6507lp_alu.v
142	Alu bug fixed. Z and N flags depend on result, so they must be attributed after result is assigned.	gabrieloshiro	5587d 03h	/t6507lp/trunk/rtl/verilog/t6507lp_alu.v
141	t6507lp_alu.v is the correct name for the alu module. File name should always be the same as the module name.	creep	5587d 03h	/t6507lp/trunk/rtl/verilog/t6507lp_alu.v