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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu.v] - Rev 161

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161 Sum and subtract were wrong when D flag was HIGH. gabrieloshiro 5564d 01h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
158 Bug 28 fixed. PHA was not coping the register to alu_a output gabrieloshiro 5566d 22h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
157 gabrieloshiro 5566d 22h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
156 Some bugs were fixed. Testbench were expecting wrong values sometimes. gabrieloshiro 5567d 00h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
154 BRK_IMP was asserting 0 to B flag.

Bug report #25 fixed.		 gabrieloshiro 5567d 04h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
152 Bug #24 from trac was fixed. gabrieloshiro 5567d 22h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
151 tah comitado! gabrieloshiro 5567d 23h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
150 Bug #24 from trac might be fixed. Processor register is working properly. gabrieloshiro 5567d 23h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
149 Bug #24 from trac might be fixed. Processor register is working properly. gabrieloshiro 5568d 00h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
148 Reset assertion was commented. It was not working properly. gabrieloshiro 5568d 00h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
145 ASL instruction fixed. For some reason the operator "<<" is not working properly. gabrieloshiro 5568d 23h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
142 Alu bug fixed. Z and N flags depend on result, so they must be attributed after result is assigned. gabrieloshiro 5569d 03h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
141 t6507lp_alu.v is the correct name for the alu module. File name should always be the same as the module name. creep 5569d 03h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v

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