OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu.v] - Rev 238

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
238 ALU file is linted. creep 5659d 16h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
234 SBC Decimal mode 100% verified. creep 5666d 16h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
233 ADC and SBC are 100% verified in regular mode. Decimal mode still missing. creep 5666d 20h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
224 Added a top level for the tests. creep 5669d 15h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
186 Testbench has a lot of new tests. gabrieloshiro 5702d 12h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
184 TXA and TYA behavior were changed. Now alu_result dont receive A value gabrieloshiro 5702d 21h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
183 STA, STY and STX should be working now gabrieloshiro 5703d 13h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
181 This time ADC decimal should be working properly and SBC (normal mode) should be back to its accurate behavior gabrieloshiro 5703d 16h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
179 STA, STY and STX fixed gabrieloshiro 5703d 19h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
178 STA, STY and STX fixed gabrieloshiro 5703d 19h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
176 RTI works for me gabrieloshiro 5703d 22h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
175 PLP and RTI should be working according to stella now. STATUS <= alu_a. gabrieloshiro 5704d 17h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
174 SBC borrow flag bug fixed... again gabrieloshiro 5704d 18h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
173 SBC bug fixed. Borrow should be working properly. gabrieloshiro 5704d 18h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
172 RTI supported to be compatible with stella gabrieloshiro 5704d 20h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
171 Removed debug messages. creep 5704d 21h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
169 ADC bugs finally fixed. gabrieloshiro 5705d 13h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
168 RTI fixed! now ALU doesn`t support RTI instruction anymore. gabrieloshiro 5705d 15h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
167 Now SBC is supposed to work. gabrieloshiro 5705d 15h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v
166 Commiting again! gabrieloshiro 5705d 15h /t6507lp/trunk/rtl/verilog/t6507lp_alu.v

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.