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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_alu_tb.v] - Rev 178

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178 STA, STY and STX fixed gabrieloshiro 5668d 16h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
176 RTI works for me gabrieloshiro 5668d 19h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
174 SBC borrow flag bug fixed... again gabrieloshiro 5669d 15h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
173 SBC bug fixed. Borrow should be working properly. gabrieloshiro 5669d 15h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
169 ADC bugs finally fixed. gabrieloshiro 5670d 11h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
165 SBC and PHP fixed! gabrieloshiro 5670d 13h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
164 ADC with decimal mode bug... is it ok now? gabrieloshiro 5670d 14h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
161 Sum and subtract were wrong when D flag was HIGH. gabrieloshiro 5670d 16h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
158 Bug 28 fixed. PHA was not coping the register to alu_a output gabrieloshiro 5673d 12h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
156 Some bugs were fixed. Testbench were expecting wrong values sometimes. gabrieloshiro 5673d 14h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
150 Bug #24 from trac might be fixed. Processor register is working properly. gabrieloshiro 5674d 13h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
149 Bug #24 from trac might be fixed. Processor register is working properly. gabrieloshiro 5674d 14h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
148 Reset assertion was commented. It was not working properly. gabrieloshiro 5674d 15h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
145 ASL instruction fixed. For some reason the operator "<<" is not working properly. gabrieloshiro 5675d 13h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
143 Modified the inputs so the alu resets. creep 5675d 15h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
140 Variable names were changed according to coding guidelines. gabrieloshiro 5675d 17h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
136 Some minor coding style changes. gabrieloshiro 5676d 14h /t6507lp/trunk/rtl/verilog/t6507lp_alu_tb.v
127 Testbench created. Simulation is almost done! Everything seems to be working fine. gabrieloshiro 5680d 18h /t6507lp/trunk/rtl/verilog/T6507LP_ALU_TestBench.v

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