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[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm.v] - Rev 108

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108 PHA and PHP are coded and simulated. creep 5580d 00h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
107 The RTS instruction is working fine. Coded and simulated. creep 5580d 01h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
105 The RTI instruction is working fine. Coded and simulated. creep 5580d 02h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
104 The BRK instruction is working. The reset vector was tested also. creep 5580d 04h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
103 Some early modifications to support the special stack instructions. creep 5580d 21h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
102 Some early modifications to support the special stack instructions. creep 5581d 00h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
101 Absolute indirect addressing mode is coded and simulated. creep 5581d 03h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
100 IDY WRITE TYPE instructions are coded and simulated. creep 5581d 04h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
96 IDY READ TYPE instructions are coded and simulated.
IDY WRITE TYPE instructions are coded but still requires simulation.		 creep 5583d 21h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
95 IDX addressing mode is also 100%, coded and simulated. creep 5584d 00h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
94 Relative addressing mode is almost 100% functional.
It just needs another test to check if the adrres_plus_index logic is not recalculating the pc in two consecutive cycles.		 creep 5584d 21h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
88 Absolute indexed mode, READ TYPE instruction when page IS crossed is coded and simulated. creep 5585d 04h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
87 Absolute indexed mode, READ TYPE instruction when no page is crossed is coded and simulated. creep 5585d 20h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
86 Zero page indexed mode is working fine. creep 5585d 23h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
83 Completed HAL checking. All the relevant warnings and errors were removed. creep 5586d 05h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
82 Did some checking with HAL and fixed 20+ warnings and errors. creep 5586d 21h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
78 ZPG coded and simulated. creep 5586d 23h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
77 ZPG coded. Simulation is halfway. creep 5586d 23h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
71 Four addressing modes are simulated: immediate, accumulator, implied and absolute.
The simulation was done using a testbench that contains a small memory inside.		 creep 5587d 00h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
70 Fixed several timing. Registered outputs working.
Only three adressing modes coded, the previous coding was erased.		 creep 5590d 20h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v

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