OpenCores
URL https://opencores.org/ocsvn/t6507lp/t6507lp/trunk

Subversion Repositories t6507lp

[/] [t6507lp/] [trunk/] [rtl/] [verilog/] [t6507lp_fsm.v] - Rev 109

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
109 PLA and PLP are coded and simulated. creep 5683d 11h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
108 PHA and PHP are coded and simulated. creep 5683d 12h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
107 The RTS instruction is working fine. Coded and simulated. creep 5683d 13h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
105 The RTI instruction is working fine. Coded and simulated. creep 5683d 13h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
104 The BRK instruction is working. The reset vector was tested also. creep 5683d 15h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
103 Some early modifications to support the special stack instructions. creep 5684d 09h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
102 Some early modifications to support the special stack instructions. creep 5684d 12h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
101 Absolute indirect addressing mode is coded and simulated. creep 5684d 15h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
100 IDY WRITE TYPE instructions are coded and simulated. creep 5684d 16h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
96 IDY READ TYPE instructions are coded and simulated.
IDY WRITE TYPE instructions are coded but still requires simulation.		 creep 5687d 08h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
95 IDX addressing mode is also 100%, coded and simulated. creep 5687d 12h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
94 Relative addressing mode is almost 100% functional.
It just needs another test to check if the adrres_plus_index logic is not recalculating the pc in two consecutive cycles.		 creep 5688d 08h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
88 Absolute indexed mode, READ TYPE instruction when page IS crossed is coded and simulated. creep 5688d 16h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
87 Absolute indexed mode, READ TYPE instruction when no page is crossed is coded and simulated. creep 5689d 08h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
86 Zero page indexed mode is working fine. creep 5689d 11h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
83 Completed HAL checking. All the relevant warnings and errors were removed. creep 5689d 16h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
82 Did some checking with HAL and fixed 20+ warnings and errors. creep 5690d 09h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
78 ZPG coded and simulated. creep 5690d 10h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
77 ZPG coded. Simulation is halfway. creep 5690d 11h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v
71 Four addressing modes are simulated: immediate, accumulator, implied and absolute.
The simulation was done using a testbench that contains a small memory inside.		 creep 5690d 12h /t6507lp/trunk/rtl/verilog/t6507lp_fsm.v

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.